From X-bit Labs: Intel Corp. has revealed details about its upcoming microprocessor for enterprise servers at the International Solid State Circuit Technology Conference. The chip will feature up to fifteen cores, all-new topology as well as enhanced RAS [reliability, availability, scalability] features. The new chip will sport up to 15 cores.
The new generation enterprise Xeon E7-8800v2 processor code-named “Ivy Town” for high-end machines has 15 dual-threaded 64-bit Ivy-Bridge cores and 37.5MB shared L3 cache. The system interface includes two on-chip DDR3 memory controllers each with two memory channels (which support 800MT/s – 1867MT/s effective frequencies for traditional DDR3 modules as well as up to 2667MT/s speeds to connect to a memory extension buffer using voltage-mode single-ended (VMSE) interface) and supports multiple system topologies.
The Ivy Town processor’s high-speed serial I/O’s includes of 40 lanes of PCI Express (2.5/5.0/8.0Gbps), four lanes of direct media interface (DMI) (2.5/5.0Gbps), and 60 lanes of QPI (6.4/7.2/8.0Gbps) interface to connect with other central processing units (CPUs).
The floorplan of the Ivy Town chip is considerably different compared to today’s multi-core chips and is driven by the ring bus routability and latency, as well as the chop requirements to different core counts. The cores and associated L3 cache are organized in columns of five with the ring bus segment embedded. The fully populated die has 15-cores in three columns, but the die can be easily re-configured to create central processing units with lower core counts. For example, the 10-core chop removes the rightmost 3rd column and its dedicated top and bottom I/Os. Since CMOS muxes embedded in the ring bus are programmed to operate in a 2 or 3 columns configuration respectively. The 6-core chop removes the 2nd and 4th rows from the 10-core die.
The processor includes 4.31 billion transistors and is manufactured using 22nm process technology. The design supports a wide array of product offerings with thermal design power ranging from 40 to 150W and frequencies ranging from 1.4 to 3.8GHz.
To to put 15 cores into 140W thermal design envelope, Intel had to implement various measures to cut general power consumption of the chip and decrease power leakage. The “Ivytown” design uses lower-leakage transistors in non-timing-critical paths, achieving 63% usage in the cores and over 90% in the non-core area. Overall, leakage accounts for about 22% of the total power at the typical process corner, quite impressive for a multi-core chip with relatively high frequency.
The “Ivy Town” processor fits into the LGA2011 form-factors, so it can possibly fit into existing Xeon E7 machines. Intel has not proclaimed when and whether the Ivytown will be released, but if it makes it to the market, this will likely happen this year.
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