TSMC: Performance-Optimized 3nm N3P Process on Track for Mass Production This Year

From AnandTech: As part of the second leg of TSMC's spring technology symposium series, the company offered an update on the state of its 3nm-class processes, both current and future. Building on the back of their current-generation N3E process, the optical shrink of this process technology, N3P, is now on track to enter mass production in the second half of 2024. Thanks to that shrink, N3P is expected to offer both increased performance efficiency as well as increased transistor density over N3E.
N3E in Production, Yielding Well

With N3E already in volume production, TSMC is reporting that they're seeing "great" yields on the second-generation 3nm-class process note. According to the company, the D0 defect density of N3E is at relative parity with N5, matching the defect rate of the older node for the same point in its respective lifecycle. This is no small feat, given the additional complexities that come with developing one last, ever-finer generation of FinFET technology. So for TSMC's bleeding-edge customers such as Apple, who just launched their M4 SoC, this is allowing them to reap the benefits of the improved process node relatively quickly.

"N3E started volume production in the fourth quarter of last year, as planned," a TSMC executive said at the event. "We have seen great yield performance on customers' products, so they did go to market as planned."

TSMC's N3E node is a relaxed version of N3B, eliminating some EUV layers and completely avoiding the usage of EUV double patterning. This makes it a bit cheaper to produce, and in some cases it widens the process window and yields, though it comes at the cost of some transistor density.

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