AMD Displays Die-Shot of Upcoming Eight-Core Orochi Processor
From X-bit Labs: Advanced Micro Devices on Wednesday displayed a die-shot of the forthcoming central processing unit (CPU) code-named Orochi, which is based on the Bulldozer micro-architecture and will be made using 32nm silicon-on-insulator process technology.
AMD Orochi is projected to be the company's next-generation high-end desktop microprocessors. The chip will feature eight processing engines, but since it is based on Bulldozer micro-architecture, those cores will be packed into four modules. Every module which will have two independent integer cores (that will share fetch, decode and L2 functionality) with dedicated schedulers, one floating point unit with two 128-bit FMAC pipes with one FP scheduler. The chip will have shared L3 cache, dual-channel DDR3 memory controller and will use HyperTransport 3.1 bus. The Orochi chips will use new AM3+ form-factor and will require brand new platforms.
The image clearly depicts four separate dual-core Bulldozer modules with unified level-two caches, various interfaces (memory, HyperTransport, etc.), rather strangely aligned level-three cache and so on. Based on the physical size of L2 caches, it can be expected that each module will have 2MB of L2, which should ensure higher single-thread performance compared to existing processors in many situations. It is unclear why the modules on the upper side of the picture are larger than the modules on the lower side of the image. Potentially, this may indicate that either certain modules will include certain additional logic or the image has been specifically altered.
Bulldozer instruction set architecture supports SSE 4.1; SSE 4.2; AVX with AMD 4-operand FMAC subset, 256-bit YMM registers and AES; XSAVE state space management and XOP instructions. Bulldozer will also support light weight profiling (LWP) technology. As indicated earlier, there are no word on 3DNow! extensions or SSE5 instruction set.
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