AMD Already Tests Next-Gen Low-Power Kabini Chip

From X-bit Labs: Advanced Micro Devices said on Thursday that it had taped out numerous of its products due next year and there are many working chips from 2013 product lineup at the company’s labs, including code-named Kabini accelerated processing unit (APU). The company promised to release the Kabini system-on-chip, which will replace current Brazos 2.0 low-power platform, in the first half of 2013. Unfortunately, nothing was said about new high-performance solutions.

“We already have working silicon for many of our new 2013 products in house, including our next-generation 28nm Kabini APU, which is the successor to our highly successful Brazos platform and our first true SoC design. We are making good progress with the bring up of Kabini, which remains on track to launch in the first half of next year,” said Rory Read, chief executive officer of AMD, during a conference call with financial analysts.

AMD Kabini will feature up to four x86 cores based on Jaguar micro-architecture, new-generation graphics adapter as well as a number of improvements related to heterogeneous processing and system architecture. Most importantly, Kabini will also integrated input/output capabilities in addition to a new memory controller, which will greatly simplify designs of netbooks, ultra-thin notebooks and other low-power devices. Kabini will be made using 28nm process technology.

In order to significantly improve performance of Jaguar-based APUs over the Bobcat-powered chips, AMD decided to go into virtually all logical directions: increase the amount of cores, boost clock-speed, add support for modern instructions, increase amount of executed instructions per clock (IPC). AMD also decided to improve power efficiency through clock gating and unit redesign in a bid to ensure lower idle power consumption compared to existing low-power designs. Jaguar features SSE4.1, SSE4.2, AES, PCLMUL, AVX, BMI, F16C as well as MOVBE. Jaguar also introduces 128-bit floating point unit (FPU) with enhancements and double-pumping to support 256-bit AVX instructions as well as an innovative integer unit with new hardware divider, larger schedulers and more out-of-order resources. AMD implemented a new CC6 state with even deeper energy economy, with each core able to go there independently.

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