Samsung Starts Mass Producing Industry’s First 3D Vertical NAND Flash

From X-bit Labs: Samsung Electronics, the world leader in advanced memory technology, today announced that it has begun mass producing the industry's first three-dimensional (3D) vertical NAND (V-NAND) flash memory, which breaks through the current scaling limit for existing NAND flash technology. The new 3D V-NAND will be used for a wide range of consumer electronics and enterprise applications, including embedded NAND storage and solid state drives (SSDs).

Samsung's new V-NAND offers a 128Gb density in a single chip, utilizing the company's proprietary vertical cell structure based on 3D charge trap flash (CTF) technology and vertical interconnect process technology to link the 3D cell array. By applying both of these technologies, Samsung's 3D V-NAND is able to provide over twice the scaling of 20nm-class planar NAND flash.

"The new 3D V-NAND flash technology is the result of our employees' years of efforts to push beyond conventional ways of thinking and pursue much more innovative approaches in overcoming limitations in the design of memory semiconductor technology. Following the world's first mass production of 3D Vertical NAND, we will continue to introduce 3D V-NAND products with improved performance and higher density, which will contribute to further growth of the global memory industry," said Jeong-Hyuk Choi, senior vice president, flash product & technology at Samsung Electronics.

For the past 40 years, conventional flash memory has been based on planar structures that make use of floating gates. As manufacturing process technology has proceeded to the 10nm-class and beyond, concern for a scaling limit arose, due to the cell-to-cell interference that causes a trade-off in the reliability of NAND flash products. This also led to added development time and costs.

Samsung's new V-NAND solves such technical challenges by achieving new levels of innovation in circuits, structure and the manufacturing process through which a vertical stacking of planar cell layers for a new 3D structure has been successfully developed. To do this, Samsung revamped its CTF architecture, which was first developed in 2006. In Samsung's CTF-based NAND flash architecture, an electric charge is temporarily placed in a holding chamber of the non-conductive layer of flash that is composed of silicon nitride (SiN), instead of using a floating gate to prevent interference between neighboring cells.

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