Intel unveils Foveros 3D chip stacking and new 10nm ‘chiplets’

From The Verge: At an Architecture Day event hosted this week, Intel articulated an unusually lucid strategy for its development of future processors, most of which will revolve around fragmenting the various elements of a modern CPU into individual, stackable “chiplets.” Intel’s big goal for late 2019 is to offer products built on what it calls Foveros 3D stacking: an industry-first implementation of stacked processing components inside a chip. We’ve already seen stacked memory; now, Intel is doing something similar with the CPU, allowing its designers to essentially drop in extra processing muscle atop an already assembled chip die. So your on-die memory, power regulation, graphics, and AI processing can all constitute separate chiplets, some of which can be stacked atop one another. The benefits of greater computational density and flexibility are obvious, but this modular approach also helps Intel skirt one of its biggest challenges: building full chips at 10nm scale.

Intel’s previous 10nm road maps have consistently and repeatedly slipped, and there’s good reason to believe that the company faces insurmountable engineering challenges on that project. An October report from SemiAccurate even suggested that Intel has canceled its 10nm plans altogether, though the grand old chipmaker denied the rumor and said it was “making good progress on 10nm.” The two may, in fact, both be true, judging from Intel’s new disclosures. On the way to Foveros, Intel suggests it will do something it calls 2D stacking, which is a separation of the various processor components into smaller chiplets, each of which can be manufactured using a different production node. Thus, Intel could deliver nominally 10nm CPUs, which will nonetheless have various 14nm and 22nm chiplet modules within them (as shown in the graphic below).

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