Samsung Initiates Production of NAND Flash with Toggle DDR2 Interface

From X-bit Labs: Samsung Electronics said on Thursday that it had started to produce multi-level cell (MLC) NAND Flash memory with toggle DDR 2.0 interface. The chip is designed to support the high-performance requirements of mobile devices such as smartphones, tablets and solid state drives (SSDs). One of the largest makers of flash memory uses 20nm-class process technology for the 64Gb devices.

The new 64Gb (8GB) MLC NAND flash chip from Samsung with toggle DDR 2.0 interface can transmit data at a bandwidth of up to 400Mb/s (50MB/s). This provides a 10-fold increase over the 40Mb/s (5MB/s) SDR NAND flash memory in widespread use today, and a three-fold boost over 133Mb/s (16.6MB/s) toggle DDR 1.0, 32Gb NAND flash memory, which Samsung was first to produce in 2009.

The high-speed 400Mbps bandwidth of toggle DDR 2.0 is expected to better support the ongoing shift toward advanced interfaces, as more mobile and consumer electronics devices requiring added performance and higher densities adopt new interfaces such as USB 3.0 and Serial ATA-600.

“With this 20nm-class, 64Gb, toggle DDR 2.0 NAND, Samsung is leading the market, which is evolving to fourth-generation smartphones and Serial ATA 6Gb/s SSDs. We will continue to aggressively develop the world's most advanced toggle DDR NAND flash solutions with higher performance and density, since we see them as vital to enabling a greater diversity of services for mobile phone users worldwide," said Wanhoon Hong, executive vice president, memory sales & marketing at Samsung Electronics.

At present it is unknown whether the new 64Gb memory chip uses 3-bit-per-cell (bpc) or 2bpc MLC design. Back in late 2010 Samsung began to manufacture 64Gb 3bpc NAND flash memory chips using 20nm-class process technology. It is not likely, however, that 3bpc multi-level cell (MLC) flash chips will actually become widespread on the market of solid-state drives due to reliability concerns unless Samsung implements special mechanisms that can sustain or even increase the amount of writes per cell in 3bpc MLC flash on the level of 10 000 times.

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