AMD's 28nm Wichita APU May Be Released Later than Expected

From X-bit Labs: While officially Advanced Micro Devices promised to release its next-generation platform for netbooks, low-cost thin notebooks and nettops in calendar 2012, it is completely unclear when exactly the company will be able to introduce its code-named Deccan platform.

Officially, the code-named Wichita accelerated processing unit (APU) is planned to be released in 2012. However, a source with knowledge of AMD's plans said that the company still has not set any exact schedule for the roll-out of its second-generation entry-level APU-based platform. In fact, AMD intends to sell its Brazos chips till Q4 2012 at least, according to the person, who decided to remain anonymous. However, it should be noted that the existing plans are not final.

AMD code-named Wichita accelerated processing unit is a pretty revolutionary design that will be the industry's first quad-core x86-based system-on-chip with built-in graphics and I/O capabilities. Wichita will integrate up to four Bobcat-class x86 cores with Turbo Core 3.0 dynamic acceleration technology, DirectX 11 graphics core, DDR3 memory controller as well as Yuba FCH [Fusion controller hub] that will support Serial ATA, PCI Express, USB and other I/O protocols. AMD Wichita, which will utilize FT2 BGA packaging, will be the heart of Deccan platform for netbooks, low-cost ultra-thin notebooks and nettops.

With four Bobcat cores and other improvements, Wichita is projected to offer significantly higher performance compared to Ontario/Zacate while maintaining roughly the same thermal design power. Naturally, with the cost below $100, the chip will encourage software developers to optimize their applications for multi-core processors as well as GPGPU technologies. Besides, Wichita with two cores will be able to significantly reduce power consumption compared to existing offerings.

Thanks to high integration and elimination of discrete FCH, AMD's Wichita/Deccan in FT2 BGA packaging will allow manufacturers of netbooks, notebooks and nettops to lower the amount of elements, trim costs and reduce sizes of their device.

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