AMD Describes Piledriver Architecture Peculiarities to Software Developers

From X-bit Labs: Advanced Micro Devices has released a document that is supposed to assist software developers to optimize their programs for AMD’s microprocessors based on Bulldozer micro-architecture and forthcoming chips. Among other things, AMD describes peculiarities of Piledriver micro-architecture as well as chips on its base, including Trinity, Vishera, Terramar and Sepang. The document also mentions Steamroller and Excavator micro-architectures

AMD has a rather strong and clear roadmap for the period of the following three years with the aim to increase performance-per-watt of its high-performance cores by approximately 10% - 15% every year. In practice, this transforms into 33% - 52% speed boost of Excavator micro-architecture compared to Bulldozer. Technologically, AMD wants to improve IPC (instructions per clock) performance and reduce power consumption at the same time, which transforms into higher clock-speeds.

Among the revelations regarding Piledriver, noted by CPU-World web-site, are increased number of entries of L1 TLB, deeper FPU load queue, FMA3, BMI, TBM and other new instructions.

Interestingly, but the maximum amount of cores inside Vishera (next-gen FX-class desktop-chip), Sepang (1-die Opteron chip for 1-2 socket servers) and Terramar (2-die Opteron MCM for 2-4 socket servers) microprocessors is considered to be ten, not eight in case of Vishera as noted earlier. Moreover, it looks like the silicon behind all three of the products seems to be very same.

Another notable news is that the AMD family 15h models 2xh chips will physically have quad-channel memory controller, which lets creation of server platforms with extreme memory bandwidth (even eight-channel memory is theoretically possible in case of 4-socket machines). Unfortunately, since Vishera is supposed to be socket AM3+ compatible, it will not support quad-channel DDR3 memory.

View: Article @ Source Site