From ExtremeTech: here’s a new set of leaks around AMD’s next-generation server CPU, codenamed Milan-X. Milan-X uses the same microarchitecture as AMD’s current Milan, but with one significant difference: Up to 768MB of L3, divided between 8 chiplets and 64 cores.
AMD’s plans to staple an extra 64MB of L3 cache per chiplet via its new V-NAND structures have been well-discussed, but these leaks — if accurate — give us some idea of what kind of trade-offs the company is contemplating between TDP, clock speed, and cache size.
There are four parts in total — a 32-core and a 24-core round things out — but the top-end and bottom-end are the most interesting.
At the high end, AMD is trading ~10 percent base clock frequency for an extra 512MB of L3. At top of the 16-core mark, the 7373X trades off ~13 percent frequency, but offers no less than 48MB of L3 cache per core (768MB / 16 cores). If Milan-X uses the same chiplet configurations as Milan, AMD is only lighting up two cores per chiplet for a CPU like this — but the company has does something similar before. AMD currently ships an eight-core CPU with 256MB of L3 in total, or 32MB of L3 per cache. AMD may be reserving V-Cache for its high-power products; most of AMD’s 16-core chips target a TDP below 240W.
Elsewhere, AMD has suggested that its V-Cache is worth ~15 percent performance, which may seem to imply the company is giving up most of its advantage by trading away base clock speed. This probably isn’t true, for several reasons. First, base clock reflects the minimal clock, not necessarily the sustained CPU clock. Second, server workloads don’t scale according to the same factors as desktop workloads in all cases.
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