From Tom's Hardware: Samsung Foundry is set to detail its third generation process technology featuring gate-all-around (GAA) transistors at the VLSI Symposium 2024 in June. The technology is called SF2, and it will be the company's initial 2nm-class fabrication process. The node is projected to offer significant improvements when it comes to performance and efficiency.
Samsung will outline key details about its SF2 fabrication technology at a session on June 19, 2024. Based on the company's own description, the upcoming node will further refine Samsung's multi-bridge channel field-effect transistor architecture with a unique epitaxial and integration process. This will enable it to increase transistor performance by 11–46 percent and reduce variability compared to an unspecified FinFET-based process technology by 26%, while decreasing leakage by about 50%.
"A product performance aware 3rd generation MBCFET (SF2) is revealed to maximize gate-all-around benefit fully by introducing unique epitaxial and integration process, which overcomes the scaling and GAA structure conflict with a product gain," the description by Samsung reads. "The product major narrow NS transistor was boosted by N/PFET +29/+46%, as well as a wide NS transistor +11/+23%. In addition, through transistor global variation reduction by 26% from FinFET, a product leakage distribution was significantly scaled by ~50%."
Business Korea reports that Samsung is not only pushing technological boundaries but is also strengthening its ecosystem for its 2nm-class fabrication process. The company is working with over 50 intellectual property (IP) partners and holds more than 4,000 IP titles, though for obvious reasons only a handful of them are aimed at GAA nodes in general and SF2 in particular. Meanwhile, earlier this year Samsung and Arm inked a deal to co-optimize Cortex-X and Cortex-A cores for Samsung's gate-all-around transistor-based manufacturing technologies.
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