From EETimes: Intel has demonstrated a general-purpose, 14 nm SerDes chip designed to reduce the size of its successful 22 nm SerDes offering by 40%, and also to cut power consumption by 20% compared to the 22 nm SerDes product.
The March 20 announcement of the 1 Gbit/s to 16 Gbit/s SerDes appeared designed to defend Intel against both long- and short-term setbacks that have allowed competitors to suggest its traditional lead in semiconductor design and manufacturing is deteriorating.
The new 14 nm SerDes design is based on that of the existing 12 Gbit/s and 28 Gbit/s SerDes built on Intel's 22 nm SerDes Tri-gate process. The newest version of Intel's general-purpose SerDes includes 10 Gbit/s to 32 Gbit/s high-speed versions and 1 Gbit/s to 10 Gbit/s low-power versions. They support a range of standard protocols for networking and I/O to connect circuit-board components in mobile or handheld devices, including USB, PCIe, Ethernet, and 10G-KR.
The low-power version also provides low standby power and support for protocols like MIPI M-PHY and USB SuperSpeed Interchip (SSIC), which are used for low-power, high-speed connections between components inside mobile and wireless devices. The high-speed versions also address OIF, 100G Ethernet, and 32 FibreChannel for high-performance networking applications.
Intel executives tout the low-power versions as "a complete foundry offering," including integration, test configuration, and system simulation. as well as orientation and protocol configurability. The size and power-use specifications demonstrate that it's possible to shrink the space and power requirements of even complex components while increasing performance, according to statements in the announcement attributed to Mark Bohr of Intel's Technology and Manufacturing Group.
It also demonstrates that "clearly, Moore's Law is alive and well," he said.
Moore's Law -- a 1965 prediction that the number of transistors that will fit on a silicon chip would double every one and a half to two years without adding significantly to cost -- hit a couple of major bumps at the same time Intel saw its dominance of the personal-computing market weaken as mobile-computing devices grew in popularity at the expense of PCs.
Between 2009 and 2012, CPU performance increased at between 10% and 20% per year, rather than the 60% predicted by Moore's Law. Switching from the 32 nm or 28 nm nodes to the 22 nm node on a 300 mm wafer increases design costs by half, process development costs by 45%, and fabrication costs by about 40%, according to a December 13, 2013, McKinsey & Co. report.
The process-development cost of dropping below 20 nm could exceed $1 billion and require updates in fabrication facilities that could cost more than $10 billion, according to the McKinsey analysis, which suggested the result could be a dramatic disruption in the economics of the semiconductor business.
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