AMD to Describe 32nm x86-64 Processor at Chip Conference

From X-bit Labs: Advanced Micro Devices plans to describe some of the features of its next-generation mobile microprocessor at the International Solid-State Circuits Conference (ISSCC) in early February, 2010. The company will not disclose all the details, which is logical, considering that its 32nm central processing units (CPUs) are only due in 2011, but some of the capabilities may be rather interesting.

One of the documents to be discussed during the ISSCC covers “a 32nm core capable of data rates above 3GHz and power consumption variable from 2.5 to 25W,” reports EETimes web-site.

"The 32nm implementation of an AMD x86-64 core occupying 9.69mm2 and containing more than 35 million transistors (excluding L2 cache), operates at frequencies >3GHz. The core incorporates numerous design and power improvements to enable an operating range of 2.5W to 25W and a zero-power gated state that make the core well-suited to a broad range of mobile and desktop products," the official document reads.

AMD did not state which of its x86-64 cores it plans to describe, which adds a mistery to the content. There are three major 32nm products incoming from AMD:

* 32nm design based on high-end Bulldozer micro-architecture, which will operate at 3GHz or higher clock-speeds.
* Low-power code-named Bobcat processor designed specifically for environments that count every watt of power.
* Highly-integrated Llano processor that features 4 x86 cores and 480 stream processors for graphics and stream computing on the same piece of silicon.

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