From Tom's Hardware: TSMC is on track to qualify its ultra-large version of chip-on-wafer-on-substrate (CoWoS) packaging technology that will offer an interposer size of up to nine reticle sizes and 12 HBM4 memory stacks in 2027, the company announced at its European Open Innovation Platform (OIP) forum this month. The new packaging method will address the most performance-hungry applications and let AI and HPC chip designers build processors the size of the palm of a hand.
TSMC introduces new process technologies every year, doing its best to meet its customers' needs for power, performance, and area (PPA) improvements. But some customers need even more performance, and for whom an EUV litho tool reticle limit of 858 mm^2 is not enough. These customers choose to use multi-chiplet solutions packaged using TSMCs CoWoS technology, and in recent years, the company offered multiple iterations of this method.
The original CoWoS enabled chip packages of around 1.5-reticle size in 2016, then evolved to 3.3-reticle size today, which enables placing eight HBM3 stacks into a package. Next up, TSMC promises 5.5-reticle size packages with up to 12 HBM4 memory stacks in 2025 – 2026. However, this pales behind the company's ultimate version of CoWoS, enabling system-in-packages (SiPs) of up to nine reticle sizes with 12 and potentially more HBM4 modules onboard.
That 9-reticle 'Super Carrier' CoWoS (offering up to 7,722 mm^2 for chiplets and memory) with 12 HBM4 stacks is planned to be qualified in 2027, so it is reasonable to expect it to be adopted in 2027 – 2028 for ultra-high-end AI processors.
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